1. Field of the Invention
This invention relates generally to the fabrication of integrated circuits and, more particularly to the fabrication of insulated gate, field effect transistor (IGFET) devices. This invention is related specifically to (IGFET) devices that have source/drain regions having two sub-regions, each sub-region with a different doping level.
2. Description of the Related Art
An insulated gate, field effect transistor (IGFET) device 5, such as a metal-oxide semiconductor field-effect transistor (MOSFET) is shown in FIG. 1. A substrate 10 has a doped well region 12, a p-doped well region that will be used for purposes of illustration. The substrate 10 has a p-doped channel region 14 that provides a conducting path between the n-doped source/drain region 16A, 16B and the n-doped source/drain region 18A, 18B. In addition, a p-doped punch-through region 20, is provided below the channel region 14. Also formed in the substrate 10 are the isolation structures 22 and 24. The gate structure of the IGFET device 5 includes a gate dielectric 26, directly over the channel region 20, and a gate electrode 28 over the gate dielectric 26. The gate structure 26, 28 can include spacers 30, 32 formed against the walls of the gate structure 26,28. An insulating layer 34 covers the substrate 10 and the gate structure 26, 28. The insulating layer 34 has vias formed therein and the vias are filled with a conducting material. The conducting material provides conducting vias 36 to source/drain (electrode) regions 16A, 16B and 18A and 18B and to the gate electrode 28. An insulating layer 38, formed over insulating layer 34, is patterned and the portions removed as a result of the patterning are filled with conducting material to provide conducting paths 40. The conducting paths 40 and the remaining insulating material 38 forman interconnect layer providing the electrical coupling between the IGFET device 5 and the remainder of the integrated circuit.
The operation of the IGFET device 5 can be understood as follows. A voltage applied to the gate electrode 28 causes a transverse field in the channel region 14. The transverse field controls (e.g., modulates) the current flow between source/drain region 16A, 16B and source/drain region 18A, 18B. The punch-through region 20 is formed to prevent parasitic effects that can occur when this region is not formed in the device 5. The spacers 30, 32 and the dual-structured, doped source/drain regions 16A, 16B and 18A, 18B address a problem generally referred to as the "hot-carrier" effect. When only one source/drain region 16A and 18A is present and is formed by doping technique aligned with the electrode structure 26,28, charge carriers from these regions can migrate into the channel region 14 and be trapped by the gate dielectric 26. These trapped charge carriers adversely affect the transverse electric field normally formed in the channel region 14 by a voltage applied to the gate electrode 28. The problem is alleviated by lightly-doping source/drain regions 16A and 18A using a technique which aligns this doping procedure with the gate structure 26, 28. Spacers 30 and 32 are next formed on the walls of the gate structure 26, 28. Source/drain regions 16B and 18B are formed by a doping procedure, resulting in source/drain doping concentrations at normal levels, that aligns the source/drain regions 16B and 18B with the spacers 30 and 32, respectively. (While this two-level doping procedure effectively eliminates the "hot-carrier" problem, the resistance between the two source/drain dual regions 16A, 16B and 18A, 18B is increased.) The isolation structures 22, 24 provide electrical insulation between the device 5 and other areas of the integrated circuit.
In providing the spacers that are used in the fabrication of the two lightly-doped source/drain sub-regions, one representative technique is to use a thick layer of silicon oxide covering the exposed surfaces of the substrate and the gate structure. A greater thickness of silicon oxide will accumulate in a comer region where the gate structure is in contact with the substrate. Thus, when an isotropic etch procedure is performed, the gate structure and the surface of substrate can be exposed while leaving a comer region of silicon oxide, generally referred to as a spacer. This spacer has the ability to prevent the penetration of ions into the substrate and can therefore be used to maintain lightly-doped source/drain regions in the vicinity of the channel regions. However, this procedure has problems associated therewith. Both the rate of formation of the silicon oxide material and the etching rate can be uncertain. This uncertainty can result in spacers having unacceptable thickness or unacceptable geometry. The undesirable properties of the spacers can result in a compromise of the structure of the two regions forming each source/drain region and ultimately in the operation of the device.